1. Field of the Invention
The present invention relates to a semiconductor memory device and more specifically to a configuration for speeding up a sense amplifier for reading selected memory cell data. More particularly, the present invention relates to a configuration for a high-speed data reading in a static semiconductor memory device.
2. Description of the Background Art
Semiconductor memory devices (simply referred to as a memory hereinafter) include a static memory (SRAM: Static Random Access Memory) having an internal circuit operating statically, a dynamic memory (DRAM: Dynamic Random Access Memory) having an internal circuit operating dynamically and having stored data required to refresh, and a non-volatile memory storing data in a non-volatile manner. These memories are used in various fields depending on their individual characteristics.
FIG. 26 schematically shows a configuration of a main part of a conventional SRAM. In FIG. 26, the conventional semiconductor memory includes normal memory cells M arranged in rows and columns. FIG. 26 representatively shows memory cells M00 to M0n to Mm0 to Mmn arranged in a matrix of (m+1) rows and (n+1) columns.
Word lines W0 to Wm are disposed corresponding to the respective rows of normal memory cells M00 to Mmn. FIG. 26 representatively shows a word line W0 arranged corresponding to normal memory cells Mm0 to Mmn, a word line Wk arranged corresponding to normal memory cells Mk0 to Mkn, and a word line Wm arranged corresponding to normal memory cells Mm0 to Mmn.
A pair of normal bit lines BT and BB are disposed corresponding to each column of normal memory cells M00 to Mmn. FIG. 26 representatively shows normal bit lines BT0 and BB0 arranged corresponding to normal memory cells M00 to Mm0, and normal bit lines BTn and BBn arranged corresponding to normal memory cells M0n to Mmn. Complementary data are transmitted through paired normal bit line BT (generically representing normal bit lines BT0 to BTn) and normal bit line BB (generically representing normal bit lines BB0 to BBn) when a normal memory cell on a corresponding column is selected.
The respective pairs of normal bit lines BT0 and BB0 to BTn and BBn are provided with bit line precharge circuits PNC0 to PNCn each responsive to a precharge signal PRC for precharging normal bit lines BT and BB in a corresponding pair to a prescribed potential (power supply voltage VDD) level. Each of these bit line precharge circuits PNC0 to PNCn includes a precharge transistor configured of a P channel MOS transistor (an insulated gate type field effect transistor) transmitting power supply voltage VDD to corresponding bit lines BT and BB when conductive, and an equalize transistor configured of a P channel MOS transistor rendered conductive in response to precharge signal PRC and electrically short-circuiting corresponding bit lines BT and BB when made conductive.
Word line drive circuits WD0 to WDm are provided corresponding to word lines W0 to Wm, respectively. These word line drive circuits WD0 to WDm drive corresponding word lines W0 to Wm to a selected state in accordance with row select signals X0 to Xm generated by decoding a row address signal (not shown). Each of these word line drive circuits WD0 to WDm in FIG. 26 is configured with cascaded inverters of two stages, by way of example.
One of these row select signals X0 to Xm is driven to H (logic high) level, and a word line corresponding to that row select signal is driven to H level. In other words, a selected word line has a voltage level at H level, and a non-selected word line has a voltage level at L (logic low) level. Therefore, in the state in which a word line is selected, the voltage level of the word line corresponding to the row that is addressed in accordance with a row address signal (not shown) is driven and held at H level, and the voltage level of the remaining word lines (non-selected word lines) is held at L level.
Column select gates PCS0 to PCSn selectively rendered conductive in response to column select signals Y0 to Yn are provided corresponding to the respective pairs of normal bit lines BT0, BB0 to BTn, BBn. Each of these column select gates PCS0 to PCSn includes P channel MOS transistors provided for the respective bit lines BT and BB. By rendering column select gates PCS0 to PCSn conductive in accordance with column select signals Y0 to Yn, a normal bit line pair arranged corresponding to a column designated by the column select signals is coupled to a sense amplifier SA.
H level data can be transmitted to the sense amplifier without a threshold voltage loss in the MOS transistor by configuring a column select gate PCS (generically representing column select gates PCS0 to PCSn) with P channel MOS transistors.
This sense amplifier SA is activated in response to activation of a sense enable signal SE and differentially amplifies the bit line potential transmitted through the selected column select gate to generate internal read data Dout.
A dummy column DSET is provided in order to generate sense enable signal SE to the sense amplifier SA. In dummy column DSET, dummy memory cells D0 to Dm are disposed sharing the rows with normal memory cells M00 to Mmn, respectively. These dummy cells D0 to Dm are respectively connected to word lines W0 to Wm arranged in corresponding rows.
Dummy bit lines DT and DB are disposed corresponding to dummy memory cells D0 to Dm. These dummy bit lines DT and DB are provided with a dummy bit line precharge circuit PDC responsive to precharge signal PRC for precharging and equalizing dummy bit lines DT and DB to a prescribed voltage (power supply voltage VDD) level. Similarly to precharge circuits PNC0 to PNCn, this dummy bit line precharge circuit PDC includes a P channel MOS transistor for equalization and P channel MOS transistors for precharging.
In dummy column DSET, an inverter buffer G190 for generating sense enable signal SE is provided for dummy bit line DT. More specifically, the internal connection of dummy memory cells D0 to Dm is set such that L level data is read onto dummy bit line DT.
The memory cells as many as those for each pair of normal bit lines BT0, BB0 to BTn, BBn are connected to dummy bit lines DT and DB. Dummy cells D0 to Dm and normal memory cells M00 to Mmn have component transistors of the same size, and the same loads are connected to dummy bit line DT and normal bit lines BB and BT. Therefore a timing at which memory cell data is read on normal bit lines BT0, BB0 to BTn, BBn can be detected by detecting the potential decrease in this dummy bit line DT. Responsively, when memory cell data is read and the potential difference between a pair of normal bit lines exceeds a prescribed value, sense enable signal SE is activated to cause sense amplifier SA to carry out a sensing operation.
FIG. 27 shows the circuit configuration of normal memory cells M00 to Mmn shown in FIG. 26. These normal memory cells M00 to Mmn have the same configuration, and therefore, FIG. 27 representatively shows a normal memory cell M.
In FIG. 27, normal memory cell M includes a P channel MOS transistor PQ1 connected between a power supply node and a storage node ML and having its gate connected to a storage node MR, a P channel MOS transistor PQ2 connected between the power supply node and storage node MR and having its gate connected to storage node ML, an N channel MOS transistor NQ1 connected between storage node ML and a ground node and having its gate connected to storage node MR, an N channel MOS transistor NQ2 connected between storage node MR and the ground node and having its gate connected to storage node ML, an N channel MOS transistor NQ3 responsive to a signal on word line W for electrically coupling storage node ML to normal bit line BT selectively, and an N channel MOS transistor NQ4 selectively rendered conductive in response to a signal on word line W and electrically coupling storage node MR to normal bit line BB when made conductive.
MOS transistors PQ1 and NQ1 form a first CMOS inverter, and MOS transistors PQ2 and NQ2 form a second CMOS inverter. These first and second CMOS inverters form an inverter latch holding data at storage nodes MR and ML.
In the configuration of normal memory cell M shown in FIG. 27, complementary data are held at storage nodes ML and MR by the first and second CMOS inverters. Specifically, one of storage nodes ML and MR is at power supply voltage VDD level and the other is at the ground voltage level.
When word line W is driven to a selected state, MOS transistors NQ3 and NQ4 are rendered conductive, and storage nodes ML and MR are electrically coupled to normal bit lines BT and BB. These normal bit lines BT and BB are precharged at power supply voltage VDD level in advance by bit line precharge circuit PNC. Therefore, out of these normal bit lines BT and BB, the potential of the normal bit line coupled to a storage node storing L level data is lowered, and the other bit line is held at power supply voltage VDD level. Sense amplifier SA senses and amplifies the potential difference between these normal bit lines BT and BB.
FIG. 28 shows the circuit configuration of dummy cells D0 to Dm shown in FIG. 26. These dummy cells D0 to Dm have the same configuration, and therefore, FIG. 28 representatively shows the circuit configuration of a single dummy cell D.
In FIG. 28, dummy cell D includes a P channel MOS transistor PQ3 connected between the power supply node and a storage node DSL and having its gate connected to the power supply node, an N channel MOS transistor NQ5 connected between storage node DSL and the ground node and having its gate connected to the power supply node, a P channel MOS transistor PQ4 connected between the power supply node and a storage node DSR and having its gate connected to the ground node, an N channel MOS transistor NQ6 connected between storage node DSR and the ground node and having its gate connected to the ground node, an N channel MOS transistor NQ7 selectively rendered conductive in response to a signal on word line W and electrically coupling storage node DSL to dummy bit line DT when made conductive, and an N channel MOS transistor NQ8 selectively rendered conductive in response to a signal on word line W and electrically coupling storage node DSR to dummy bit line DB when conductive.
In the configuration of dummy cell D shown in FIG. 28, MOS transistors PQ3 and NQ6 are fixed at an off-state or non-conductive state, and MOS transistors PQ4 and NQ5 are fixed at an on-state or conductive state. Therefore, storage node DSL is fixed at L level and storage node DSR is fixed at H level.
When word line W is selected and has its voltage level rising, MOS transistors NQ7 and NQ8 are rendered conductive, and storage nodes DSL and DSR are electrically coupled to dummy bit lines DT and DB, respectively. Since storage node DSL is at L level, the current flows from dummy bit line DT precharged to the power supply voltage level by dummy precharge circuit PDC through MOS transistors NQ7 and NQ5 to the ground node, and the potential level of this dummy bit line DT is lowered. On the other hand, dummy bit line DB is held at the power supply voltage level since storage node DSR is at the power supply voltage VDD level and there is no discharging path. When the potential of this dummy bit line DT exceeds an input logical threshold of inverter buffer G190 shown in FIG. 26, sense enable signal SE from this inverter buffer G190 is activated.
FIG. 29 shows an exemplary configuration of sense amplifier SA shown in FIG. 26. In FIG. 29, sense amplifier SA includes a P channel MOS transistor PS2 connected between the power supply node and an internal node SL and having its gate connected to internal node SR, a P channel MOS transistor PS3 connected between the power supply node and internal node SR and having its gate connected to internal node SL, an N channel MOS transistor NS0 receiving sense enable signal SE at its gate, an N channel MOS transistor NS1 connected between internal node SL and MOS transistor NS0 and having its gate connected to internal node SR, an N channel MOS transistor NS2 connected between internal node SR and MOS transistor NS0 and having its gate connected to internal node SL, a P channel MOS transistor PS0 transferring (coupling) an input signal (node) /NB to internal node SL in accordance with sense enable signal SE, and a P channel MOS transistor PS1 transferring (coupling) an input signal (node) /NT to internal node SR in response to sense enable signal SE. Internal read data Dout is output from internal node SR.
Input signals /NB and /NT are signals corresponding to the potential levels on normal bit lines BB and BT, respectively, when a column is selected. Where reference characters /NT and /NB indicate input nodes, these nodes /NT and /NB are internal read data lines to which selected bit lines are coupled through a column select gate. In the following description, reference characters /NT and /NB will be used to indicate input signals to sense amplifier SA.
In this sense amplifier SA, when sense enable signal SE is at L level, MOS transistors PS0 and PS1 are turned on, and input signals /NB and /NT are transmitted to internal nodes SL and SR. In this state, MOS transistor NS0 is turned off, a path through which operating current flows is shut off in the circuit configured of MOS transistors PS2, PS3, NS1 and NS2, and the sensing operation is not carried out.
When sense enable signal SE goes to H level, MOS transistors PS0 and PS1 are turned off, and internal nodes SL and SR are isolated from the signal input nodes (internal data lines). In this state, MOS transistor NS0 is turned on, sense amplifier SA is activated, and one of internal nodes SL and SR is driven to the ground voltage level while the other is driven to the power supply voltage VDD level.
In sense amplifier SA shown in FIG. 29, after the input signals, that is, bit line voltages /NB and /NT are confined in internal nodes SL and SR, sense amplifier SA is activated to carry out the sensing operation. P channel MOS transistors PS2 and PS3 have their gates and drains cross-coupled, and N channel MOS transistors NS1 and NS2 have their gates and drains cross-coupled. Cross-coupled MOS transistors PS2 and PS3 hold a higher potential internal node of internal nodes SL and SR at the power supply voltage VDD level, and cross-coupled MOS transistors NS1 and NS2 drive the lower potential internal node of internal nodes SL and SR to the ground voltage level.
Internal nodes SL and SR are usually driven to the power supply voltage VDD level by a data line precharge circuit (not shown) when sense enable signal SE is at L level. This sense amplifier SA has the voltage level at internal node SL or SR lowered in accordance with the transmitted bit line potential, and differentially amplifies that potential difference between the internal nodes for latching.
This sense amplifier SA shown in FIG. 29 is called a latch type sense amplifier as it latches the amplified data at internal nodes SL and SR while being activated. The following advantages are provided by using this latch type sense amplifier in place of a general, current mirror type sense amplifier. As semiconductor integrated circuits is increased in integration degree with finer process techniques, reduced power consumption is strongly demanded in view of prevention of malfunctions due to heat generation and others. Memory such as SRAM is not exceptional in this regard. When a current mirror type sense amplifier is used, a current source is required and constantly current flows in holding data, increasing undesirable current consumption. On the other hand, in the case of a latch type sense amplifier, current only temporarily flows at the time of a sensing operation in which the voltages at internal nodes SL and SR are differentially amplified, and current does not flow after these internal nodes SL and SR are driven to the power supply voltage VDD and ground voltage levels. Therefore, power consumption can be reduced significantly as compared with the current mirror type sense amplifier.
By isolating these internal nodes SL and SR from the signal input nodes at the time of the sensing operation, this sense amplifier SA is required only to drive internal nodes SL and SR and thus can drive a small load at high speed and carry out the sensing operation at high speed with low power consumption.
FIG. 30 is a signal waveform diagram representing the operation of SRAM shown in FIGS. 26 to 29 in reading data. In the following, referring to FIG. 30, the operation of memory (SRAM) shown in FIGS. 26 to 29 will be described.
It is assumed that precharge signal PRC is a signal generated in synchronization with a clock signal (not shown) and this SRAM is a clock synchronous type memory. It is further assumed that data is read out while this clock signal is being at H level and the bit line is precharged while the clock signal is being at L level.
While the clock signal is at L level, precharge signal PRC is also at L level, all precharge circuits PDC and PNC0 to PNCn are activated, and all dummy bit lines DT and DB and normal bit lines BT0, BB to BTn, BBn are precharged to the power supply voltage VDD level, for initialization of the reading operation.
When precharge signal PRC rises to H level, all precharge circuits PDC and PNC0 to PNCn are inactivated, and all dummy bit lines DT and DB and normal bit lines BT0, BB0 to BTn, BBn enter a floating state at the power supply voltage VDD level. Furthermore, in response to the rising of the clock signal, a row select signal is generated in accordance with an externally applied address signal, one of row select signals X0 to Xm shown in FIG. 26 is driven to H level, and a corresponding word line is responsively driven to a selected state. As shown in FIG. 30, assuming that word line Wk is selected, the voltage level of this selected word line Wk goes to H level.
In parallel with this row select operation, a column select operation is carried out such that one of column select signals Y0 to Yn is driven to a selected state in accordance with a column address signal (not shown), a corresponding column select gate of column select gates PCS0 to PCSn attains an on to state, and a normal bit line corresponding to the selected column is coupled to sense amplifier SA. The selection of column and row causes a single normal memory cell M to be selected. Now, consider a case where normal memory cell Mk0 is selected. It is further assumed that in this selected normal memory cell Mk0, storage nodes ML and MR shown in FIG. 27 store data at H level and L level, respectively. In this case, the voltage level on normal bit line BT0 to which storage node ML is connected is unchanged at H level of the precharge level, while the potential on normal bit line BB0 to which storage node MR is connected is gradually lowered since the potential on normal bit line BB0 is discharged through transistors NQ4 and NQ2 of the selected normal memory cell Mk0.
On the other hand, in dummy column DSET, dummy cells D0 to Dm configured with transistors having the same size as those of the normal memory cell are connected to dummy bit lines DT and DB. The number of dummy cells D0 to Dm connected to dummy bit lines DT and DB is equal to the number of normal memory cells connected to normal bit lines BT and BB. Therefore, in dummy column DSET, the potential of dummy bit line DT is lowered due to discharging through MOS transistors NQ7 and NQ5 shown in FIG. 28. The rate at which the potential of this dummy bit line DT is lowered is equal to the rate at which the potential of the normal bit line is lowered, as the normal bit line in the selected column has the same load as dummy bit line DT.
Here, it is assumed that the input logical threshold of inverter buffer G190 provided in this dummy column DSET is set at VDD/2. At the time t0 shown in FIG. 30, when the potential of dummy bit line DT reaches VDD/2, sense enable signal SE from inverter buffer G190 is driven to H level and sense amplifier SA is activated.
When sense enable signal SE is at L level, the potential difference between the selected normal bit lines BT0 and BB0 is transmitted to the internal node of sense amplifier SA, so that a sufficiently large potential difference is formed also in internal nodes SL and SR of sense amplifier SA. When sense enable signal SE goes to H level, sense amplifier SA is activated and carries out the sensing operation while confining the charges in internal nodes SL and SR.
When the clock signal falls to L level and precharge signal PRC goes to L level, the row select operation is completed, the selected word line Wk is driven to a non-selected state, and the voltage levels on bit lines BT0 and BB0 and dummy bit lines DT and DB are driven to H level again by precharge circuits PDC and PNC0 to PNCn. When the potential level of dummy bit line DT rises, sense enable signal SE from inverter buffer G190 goes to L level, thereby completing the sensing operation. In FIG. 30, sense enable signal SE is shown being inactivated after both dummy bit lines DT and DB are precharged to H level. This is to increase the duration of the activation period of sense enable signal SE to ensure the sufficient latching period of sense amplifier SA for reliably reading out internal data. This setting of activation duration period of sense enable signal SE is achieved by applying sense enable signal SE to sense amplifier SA through a falling delay circuit (not shown).
The following advantages can be provided by activating sense enable signal SE using dummy column DSET described above.
Specifically, latch type sense amplifier SA has a characteristic of a large gain, in addition to its advantage that DC current does not flow after the data amplifying operation. Sense amplifier SA is able to sense even slighter potential difference between the bit lines, as its gain is larger. In the latch type sense amplifier SA, however, once erroneous data is sensed and amplified, that sensed/amplified data can not be corrected.
Therefore, when the sensing operation is started before the potential difference between the bit lines becomes large enough, data may not be sensed correctly due to variations in characteristics of the transistors forming this sense amplifier SA and noises superimposed on the bit line. In order to prevent such erroneous reading, the sensing operation is started by detecting a time point at which the bit line potential, that is, the potential difference between sense amplifier internal nodes SL and SR becomes large enough using dummy column DSET.
More specifically, dummy cell D (D0 to Dm) has a component transistor having the same size as the transistors of normal memory cell M. Furthermore, the parasitic capacitance of dummy bit line DT is also the same as that of normal bit lines BT and BB. Therefore, the potential changing rate in dummy bit line DT is the same as the potential changing rate in normal bit line BT or BB. Furthermore, dummy cell D and normal memory cell M are also the same in delay time required to select a word line, since they share a word line. Therefore, when sense amplifier SA starts the sensing operation, the potential difference is VDD/2also in the normal bit line pair as similar to dummy bit lines DT and DB, and this potential difference is transmitted to sense amplifier SA. It is therefore ensured that at the time of the sensing operation by sense amplifier SA, the potential difference between the bit lines can be set large enough and a sufficient sense margin is secured, so that erroneous reading can be prevented.
Since latch type sense amplifier SA is great in gain, erroneous reading may not occur as far as the potential difference between the bit lines is on the order of 100 mV, even in consideration of the effects of variations in transistor characteristics and noises. However, as shown in FIG. 31, where power supply voltage VDD is 1.8V, sense enable signal SE is activated at the time point t0 at which the potential difference between bit line pair is 0.9V. Sense amplifier SA can carry out the sensing operation at the time ta to generate the internal read data, since the sensing operation is carried out accurately as far as the potential difference AVs between the bit line pair is 100 mV.
Therefore in the conventional configuration, the internal read data can not be generated at high speed because an excessively large sense margin is set. In other words, the internal reading operation is delayed by the time period from the time ta to the time to shown in FIG. 31.
In order to set this internal reading timing faster, it can be considered to set the input logical threshold of inverter buffer G190 shown in FIG. 26 at a higher voltage. The input logical threshold of the inverter buffer is adjusted by adjusting the sizes and threshold voltages of the transistors as its component. Therefore, variations in transistor characteristics cause variations in the input logical threshold, resulting in that it becomes impossible to activate the sense enable signal accurately in accordance with the potential difference between the dummy bit line pair, or the normal bit line pair while ensuring the sensing margin.
An object of the present invention is to provide a semiconductor memory device in which a sensing operation starting timing can be set faster accurately in accordance with a potential on a dummy bit line.
Another object of the present invention is to provide a semiconductor memory device in which a potential difference between bit line pair at the start of a sensing operation can be set at a required minimum potential difference.
A further object of the present invention is to provide a semiconductor memory device in which data can be read out at high speed and accurately.
A semiconductor memory device in accordance with the present invention includes: a plurality of normal cells arranged in rows and columns; a plurality of dummy cells arranged sharing rows with these plurality of normal cells and divided into a plurality of blocks in a column extending direction; a plurality of normal bit lines arranged corresponding to columns of the normal cells, each having a normal cell on a corresponding column connected; a plurality of divided dummy bit lines arranged corresponding to respective blocks in the column of dummy cells, each having dummy cells in a corresponding block connected; a sense amplifier sensing and amplifying data in a selected cell of the normal cells; and a sense control circuit responsive to a potential change in any one of the plurality of divided dummy bit lines for activating the sense amplifier.
The dummy cells are arranged sharing rows with the normal memory cells, and the dummy bit line arranged corresponding to these dummy cells is divided in the column extending direction. By detecting the potential change in these divided dummy bit lines to activate the sense amplifier, it is possible to make the load on the divided dummy bit line smaller than the load on the normal bit line. It is possible to make a potential changing rate in this divided dummy bit line greater than a potential changing rate in the normal bit line and to thus activate the sense amplifier at a faster timing. Therefore, a sensing operation can start when a potential difference between the normal bit lines is small, and the sensing operation can be carried out with a required minimum sense margin, thereby allowing a high-speed and accurate reading operation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.